Boolflow Help

⚡What is Boolflow?

Boolflow is a free, browser-based digital logic circuit simulator. No installation, no account — open the site and start building circuits immediately.

You can place logic gates, connect them with wires, toggle input switches, and watch signals propagate through the circuit in real time. Boolflow supports combinational logic, sequential circuits (flip-flops, counters), multi-layer canvases, and programmable logic modules (PLM).

Built-in export tools let you convert any circuit to Verilog, VHDL, or C++ source code with one click.

🛠️Your first circuit

The fastest way to learn Boolflow is to build a simple AND gate circuit from scratch. It takes about two minutes.

1. 1Open the "Basic" tab in the top bar and click the AND chip. The AND gate appears on the canvas.
2. 2Switch to the "I/O" tab. Click INPUT twice — two input switches are placed. Then click OUTPUT once.
3. 3Hover over INPUT-1 until a small circle appears on its right edge. Drag from that circle to the top-left port of the AND gate. Repeat for INPUT-2 → bottom-left port of AND.
4. 4Drag from the right port of AND → left port of OUTPUT.
5. 5Click the INPUT nodes to toggle them between 0 and 1. OUTPUT lights up green only when both inputs are 1 — that is AND logic.

🔵Adding elements

The top bar contains two rows. The first row has category tabs: Basic, I/O, Triggers, Arithmetic, Plexers, Memory, Layers, PLM. Click a tab to browse its elements.

The second row (the chip strip) shows all elements of the selected category. Click any chip to place it on the canvas at a random position.

• Drag & drop: drag a chip from the strip and release it anywhere on the canvas — the element appears exactly where you drop it.
• On mobile: the chip strip and the tab row both scroll horizontally. Swipe left or right to browse all elements.

🔗Connecting blocks

Hover over any node — small circles (port handles) appear on its left (inputs) and right (outputs) edges. Drag from an output handle to an input handle of another node to draw a wire.

A wire always flows from output → input. One output can feed multiple inputs (fan-out). One input accepts only one wire.

• To delete a wire: triple-click it.
• Wires route automatically — no manual path drawing needed.
• Green wire / handle = signal is 1. Grey = signal is 0. Orange ? = disconnected or unknown.

📡Signal values: 0, 1 and ?

Boolflow uses three signal levels:

• 0 — logic low. Represented by grey handles and wire color.
• 1 — logic high. Represented by green handles and badges.
• ? — unknown or disconnected. Appears when a required input has no wire connected. Any gate with a ? input also outputs ?.

🖱️Interacting with nodes

Most interactions happen directly on the canvas:

• Click INPUT — toggles between 0 and 1.
• Click CLOCK — starts or stops the clock generator.
• Drag any node — moves it freely on the canvas.
• Triple-click a node — deletes the node and all its wires.
• Triple-click a wire — deletes only that wire.
• Drag on empty canvas — draws a selection box. All nodes inside are selected.
• Ctrl+C / Ctrl+V — copy and paste selected nodes (wires between them are included). Paste offsets by 40 px.
• Ctrl+Z / Ctrl+Y — undo / redo (up to 60 steps).
• Double-click VIA or Label node — opens rename dialog.

⌨️Keyboard shortcuts

• Ctrl+Z — undo
• Ctrl+Y — redo
• Ctrl+C — copy selected nodes
• Ctrl+V — paste copied nodes
• Delete — delete selected nodes and wires
• Triple-click node — delete node + its wires
• Triple-click wire — delete wire
• Click INPUT — toggle 0 / 1
• Click CLOCK — start / stop
• Double-click VIA / Label — rename
• Scroll — zoom in / out
• Middle-button drag — pan the canvas

🗂️Layers — multi-layer canvas

Boolflow supports up to 4 independent canvas layers (L1–L4), similar to copper layers on a PCB. Each layer has its own set of nodes and wires.

Switch layers using the L1–L4 panel on the left side of the canvas. The active layer is highlighted in its colour; a colour stripe appears along the bottom edge of the canvas.

Elements on different layers do not interact unless connected through a VIA element.

🔩VIA — cross-layer connections

A VIA is a special element (found in the Layers tab) that passes a signal from one layer to another.

• Sender: place a VIA on one layer and connect a wire to its input.
• Receiver: place a VIA with the same name on a different layer without connecting its input — it automatically outputs the sender's signal.
• Naming: double-click a VIA node to rename it. All VIAs with the same name form one electrical net across all layers.
• Coloured shortcuts in the Layers tab (● L1 … ● L4) instantly place a pre-named, pre-coloured VIA for the target layer.

⏱️CLOCK and edge-triggered elements

The CLOCK node emits a periodic square wave at a configurable frequency (Hz). Click it to start or stop.

Flip-flops (D, JK, T) and counters (CNT4, DCNT4, UDCNT4) react to the rising edge (0→1 transition) of the clock signal.

EDGE_DET outputs a 1-cycle pulse on a rising edge; FALL_DET on a falling edge. CLK_DIV divides the clock frequency by 2.

CLOCKs run on all layers simultaneously.

🧩PLM — Programmable Logic Module

PLM blocks (PLM6–PLM20) have a configurable number of inputs and outputs (3–10 inputs, 2–8 outputs). Click the ✎ button inside the node to open the formula editor.

Each output is assigned a boolean expression using: & (AND), | (OR), ! (NOT), ^ (XOR), and parentheses. Signal names match the input labels you define.

📤Code export (Verilog / VHDL / C++)

Three export formats are available in the toolbar, all operating on the active layer:

• Verilog — exports synthesisable Verilog (IEEE 1364). Modes: module only / + testbench (up to 256 input vectors, compatible with EDA Playground).
• VHDL — exports VHDL (IEEE 1076 / NUMERIC_STD). Modes: entity only / + testbench.
• C++ — exports a C++11 function using bool and uint8_t types. Topological ordering ensures correct statement sequence. Modes: function only / + main() (prints a truth table).
• Only combinational elements are exported. Sequential elements (flip-flops, counters, CLOCK) are skipped with a warning.

📊Truth Table

Click the "Truth Table" button in the toolbar to instantly compute and display the truth table for the active layer.

• All combinations of INPUT values are tested (up to 10 inputs = 1024 rows).
• Output values are shown in real time — green = 1, grey = 0, orange ? = disconnected.
• Click "Export CSV" to download the table as a spreadsheet-compatible file.

💾Saving and loading

Boolflow saves schemes as local files on your computer — no server or account required.

• Save — enter a name and click Download. A .boolflow.json file is saved to your downloads folder. All 4 layers are included.
• Load — click "Open file…" and select a previously saved .boolflow.json. The scheme loads instantly.
• Both v1.0 and v2.0 file formats are supported.

🔍Circuit integrity check

Click the "Check" button (red, in the toolbar) to scan the active layer for wiring problems.

• Missing input — a node has an input port with no wire connected (outputs ? during simulation).
• Floating output — a node's outputs are not connected to anything.
• After the check, all problematic nodes are selected on the canvas. A banner above the toolbar shows the issue count.

📚Built-in examples

Click the "Examples" button in the toolbar to open the example gallery. Each example is a ready-made circuit that you can load onto any layer and then study or modify.

• Half Adder (gate-level)
• Full Adder (component)
• 2:1 Multiplexer
• 4-bit Adder
• 3:8 Decoder
• 8:3 Priority Encoder
• 4-bit Counter
• 1-bit ALU
• SR Latch, D Latch, D / JK / T Flip-Flops
• 4-bit Register, Shift Register, Comparator, and more

📦Elements reference