Half Adder

A + B → Sum, Carry (gate-level)

Full Adder

A + B + Cin → Sum, Cout

2:1 Multiplexer

S=0 → Y=D0, S=1 → Y=D1

4-bit Adder

A[3:0] + B[3:0] + Cin → S[3:0], Cout

3:8 Decoder

EN + A[2:0] → Y[7:0]

8:3 Priority Encoder

I[7:0] → O[2:0] + GS

4-bit Counter

CLOCK → Q[3:0] (counts up)

ALU (1-bit)

Op: 00=ADD 01=AND 10=OR 11=XOR

SR Latch

S=Set, R=Reset → Q, ~Q

D Latch

EN=1 → Q follows D

D Flip-Flop

CLK rising edge → Q = D

JK Flip-Flop

J=1,K=0→Set · J=0,K=1→Reset · J=K=1→Toggle

4-bit Register

CLK latches D[3:0] → Q[3:0]

4-bit Shift Register

CLK shifts SI into Q[3:0]

4:1 Multiplexer

S[1:0]: 00→I0 01→I1 10→I2 11→I3

Full Subtractor

A - B - Bin → Diff, Bout

4-bit Comparator

A[3:0] vs B[3:0] → EQ, GT, LT

Binary → Gray Code

B[3:0] → G[3:0]

Parity Checker

A[3:0] → ODD, EVN

7-Segment Display

BCD 4-bit → visual digit 0–9